Historically, band pass filters were used to selectively amplify periodic signals in noise. This technique has the limitation that, if the filter bandwidth is made extremely small to improve noise rejection, the filter will have a tendency to "ring". Such resonant response makes a narrow band filter unsuitable for some types of signal processing situations. If the filter bandwidth is made relatively wide to avoid the ringing problem, then the noise rejection performance of the filter is degraded.
A second technique for detecting periodic signals in noise involves the use of a phase locked loop (PLL). The PLL is a closed loop control system consisting of a phase difference-to-voltage converter which drives a voltage-to-frequency converter which, in turn, provides a second input to the phase difference-to-voltage converter. While the PLL technique of detecting signals in noise works well in some applications, it is complex and less efficient than other techniques in certain other applications.
A third technique for detecting periodic signals in noise involves the use of a synchronous demodulator (SD). In the SD technique, a periodic switching function in synchronism with the periodic signal to be detected, i.e., a clock, is used to provide a switching modulation of the noisy periodic input signal. The resulting modulated signal is customarily filtered through a low pass filter, leaving only the dc component of the modulation process at the output of the filter. The magnitude of the dc component is proportional to the amplitude of the fundamental frequency component of the periodic signal to be detected. The SD process is equivalent to the time cross correlation, at zero time delay, of a noisy signal with a square wave having the same period as that of the fundamental period of the signal.
Numerous SD circuits have been devised for the purpose of synchronously detecting periodic signals in noise. A typical synchronous demodulator circuit consists of an amplifier, a switch, and a low pass filter. The gain of the amplifier can be switched alternately, for example, from +1 to -1, depending on the position of the switch, which is operated in synchronism with the input periodic signal to be detected. The positive and negative gains need not be one, as long as they are equal. In practice the switch customarily takes the form of a solid state switching circuit, employing either a JFET or a CMOS pass element. The operation of the electronic switch is customarily controlled by a logic input signal. Whatever the details of the switching element, it must provide the switching function described above. Usually some adjustment to correct for phase errors must be provided. The resultant demodulated signal at the output of the amplifier is a full-wave rectified version of the input signal, consisting of a series of positive half-sine loops. The resultant full-wave rectified signal is passed through a low pass filter, which attenuates the ac components of the full wave rectified signal and passes the dc component unattenuated. The bandwidth of the filter, e.g., an R-C circuit, would be somewhat less than the frequency of the periodic signal. The rectified output from the amplifier and the dc output of the LPF have amplitudes which are proportional to the amplitude of the original incoming sinusoidal signal. The process may be thought of as the linear multiplication of the input signal by a square wave signal of the same frequency, resulting in the production of Fourier frequency components at multiples of the signal frequency and at zero frequency. The low pass filter selectively passes the zero frequency component while attenuating all higher frequency components of the signal. Because the switch is operated in synchronism with the input signal, the signal is detected and a dc output is produced at the output of the LPF. Because any random noise at the input exhibits random phase with respect to the periodic operation of the switch, the low pass filter tends to average this random noise component to zero. The same is true for periodic input signals which are not phase coherent with the switching of the switch.
Any dc level superimposed on the periodic input signal results in the production, at the output, of a square wave component at the clock frequency. The low pass filter must be carefully designed to suppress, as much as possible, this square wave component, as well as the periodic components resulting from the full wave rectification of the input signal so that precise measurements can be made of the dc value of the low pass filter output. Regardless of the filter design, there will be a periodic component at the output which can limit the signal-to-noise ratio. Thus, the prior art SC produces an output signal having residual ac components resulting from two sources; the square wave signal produced at the output by any dc component at the input, and the full wave rectification signal at the output produced by the rectification function of the circuit on the periodic signal itself. Because a dc or very slowly varying ac signal is required for control purposes, an LPF is required at the SD output. The choice of the filter rise time or bandwidth involves a tradeoff. If the low pass filter rise time is made very large, the ripple may be attenuated to any degree desired, but the filter would have an unacceptably long rise time. If the filter time constant is made very small, it may have an acceptable rise time, but would not sufficiently attenuate the ripple components. Thus, the prior art SD will inherently produce ac components at the output which must be filtered, but any filter selection involves the above-described tradeoff. Therefore, in a practical sense, the prior art SD produces a control signal with significant errors, or alternatively, a control signal which is limited in response time.
Recently, a synchronous demodulator has been developed which includes a differential amplifier with two identical channels, one to each input where each channel receives an input signal which is switched in synchronism with a clock signal. In one embodiment of this synchronous demodulator, dc offsets at the input were eliminated from the output. There was a substantial reduction in ripple due to periodic components in the input signal. In a somewhat more complex embodiment, substantially all ripple due to periodic components in the input signal were eliminated. While these substantive problems have been addressed in this recent synchronous demodulator, the channels include averaging and hold functions which are carried out by RC circuitry that exhibit a finite rise time which may require an undesirable amount of time to change value, and the capacitors may introduce errors due to charge injection.